The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller (µC) which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to One-Time Programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.
The original AVR MCU was developed at a local ASIC house in Trondheim, Norway, where the two founders of Atmel Norway were working as students. It was known as a μRISC (Micro RISC). When the technology was sold to Atmel, the internal architecture was further developed by Alf and Vegard at Atmel Norway, a subsidiary of Atmel founded by the two architects.
Atmel says that the name AVR is not an acronym and does not stand for anything in particular. The creators of the AVR give no definitive answer as to what the term “AVR” stands for.
Note that the use of “AVR” in this article generally refers to the 8-bit RISC line of Atmel AVR Microcontrollers.
Among the first of the AVR line was the AT90S8515, which in a 40-pin DIP package has the same pinout as an 8051 microcontroller, including the external multiplexed address and data bus. The polarity of the RESET line was opposite (8051’s having an active-high RESET, while the AVR has an active-low RESET), but other than that, the pinout was identical.
 Device overview
The AVR is a Modified Harvard architecture machine with program and data stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.
 Basic families
AVRs are generally classified into five broad groups:
- tinyAVR — the ATtiny series
- 0.5–8 kB program memory
- 6–32-pin package
- Limited peripheral set
- megaAVR — the ATmega series
- 4–256 kB program memory
- 28–100-pin package
- Extended instruction set (Multiply instructions and instructions for handling larger program memories)
- Extensive peripheral set
- XMEGA — the ATxmega series
- 16–384 kB program memory
- 44–64–100-pin package (A4, A3, A1)
- Extended performance features, such as DMA, “Event System”, and cryptography support.
- Extensive peripheral set with DACs
- Application specific AVR
- megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc.
- Atmel At94k FPSLIC (Field Programmable System Level Integrated Circuit), an AVR core on-die with an FPGA. The FPSLIC uses SRAM for the AVR program code, unlike all other AVRs. Partly due to the relative speed difference between SRAM and flash, the AVR core in the FPSLIC can run at up to 50 MHz.
 Device architecture
Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data (or code) memory, or memory-mapped devices. All devices have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips.
 Program memory (flash)
Program instructions are stored in non-volatile flash memory. Although they are 8-bit MCUs, each instruction takes one or two 16-bit words.
The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64 kB of flash, however the ATmega32x has only 32 kB).
There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash.
 Internal data memory
 Internal registers
In most variants of the AVR architecture, the working registers are mapped in as the first 32 memory addresses (000016-001F16) followed by the 64 I/O registers (002016-005F16).
Actual SRAM starts after these register sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case the memory mapped I/O registers will occupy a portion of the SRAM address space.)
Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM.
In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA’s working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (000016-0FFF16). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space which can be used optionally for mapping the internal EEPROM to the data address space (100016-1FFF16). The actual SRAM is located after these ranges, starting at 200016.
Almost all AVR microcontrollers have internal Electrically Erasable Programmable Read Only Memory (EEPROM) for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed.
In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU’s addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions which makes EEPROM access much slower than other internal RAM.
However, some devices in the SecureAVR (AT90SC) family  use a special EEPROM mapping to the data or program memory depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space.
Since the number of writes to EEPROM is not unlimited — Atmel specifies 100,000 write cycles in their datasheets — a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if contents need to be changed.
 Program execution
Atmel’s AVRs have a two stage, single level pipeline design. This means the next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers.
 Instruction set
The AVR Instruction Set is more orthogonal than those of most eight-bit microcontrollers, in particular the 8051 clones and PIC microcontrollers with which AVR competes today. However, it is not completely regular:
- Pointer registers X, Y, and Z have addressing capabilities that are different from each other.
- Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31.
- I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63.
- CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note that CLR is pseudo-op for EOR R, R; and SER is short for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.)
- Accessing read-only data stored in the program memory (flash) requires special LPM instructions; the flash bus is otherwise reserved for instruction memory.
Additionally, some chip-specific differences affect code generation. Code pointers (including return addresses on the stack) are two bytes long on chips with up to 128 kBytes of flash memory, but three bytes long on larger chips; not all chips have hardware multipliers; chips with over 8 kBytes of flash have branch and call instructions with longer ranges; and so forth.
The mostly-regular instruction set makes programming it using C (or even Ada) compilers fairly straightforward. GCC has included AVR support for quite some time, and that support is widely used. In fact, Atmel solicited input from major developers of compilers for small microcontrollers, to determine the instruction set features that were most useful in a compiler for high-level languages.
 MCU speed
The AVR line can normally support clock speeds from 0-20 MHz, with some devices reaching 32 MHz. Lower powered operation usually requires a reduced clock speed. All recent (Tiny and Mega, but not 90S) AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Some AVRs also have a system clock prescaler that can divide down the system clock by up to 1024. This prescaler can be reconfigured by software during run-time, allowing the clock speed to be optimized.
Since all operations (excluding literals) on registers R0 – R31 are single cycle, the AVR can achieve up to 1 MIPS per MHz, i.e. an 8 MHz processor can achieve up to 8 MIPS. Loads and stores to/from memory take 2 cycles, branching takes 3 cycles. Branches in the latest “3-byte PC” parts such as ATmega2560 are one cycle slower than on previous devices.
AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are sold under various names that share the same basic core but with different peripheral and memory combinations. Compatibility between chips in each family is fairly good, although I/O controller features may vary.
See external links for sites relating to AVR development.
Current AVRs offer a wide range of features:
- Multifunction, bi-directional general purpose I/O ports with configurable, built-in pull-up resistors
- Multiple internal oscillators, including RC oscillator without external parts
- Internal, self-programmable instruction flash memory up to 256 kB (384 kB on XMega)
- In-system programmable using serial/parallel low-voltage proprietary interfaces or JTAG
- Optional boot code section with independent lock bits for protection
- On chip debugging (OCD) support through JTAG or debugWIRE on most devices
- The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on GPIOs. These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP or HVSP. By default, AVRs with JTAG come with the JTAG interface enabled.
- debugWIRE uses the /RESET pin as a bi-directional communication channel to access on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin.
- Internal data EEPROM up to 4 kB
- Internal SRAM up to 8 kB (32 kB on XMega)
- External 64 kB little endian data space on certain models, including the Mega8515 and Mega162.
- The external data space is overlaid with the internal data space, such that the full 64 kB address space does not appear on the external bus. An accesses to e.g. address 010016 will access internal RAM, not the external bus.
- In certain members of the XMEGA series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16 MB of data memory to be directly addressed.
- AVR’s generally do not support executing code from external memory. Some ASSP’s using the AVR code do support external program memory.
- 8-Bit and 16-Bit timers
- PWM output (Dead time generator on some devices)
- Input capture
- Analog comparator
- 10 or 12-Bit A/D converters, with multiplex of up to 16 channels
- 12-bit D/A converters
- A variety of serial interfaces, including
- Brownout detection
- Watchdog timer (WDT)
- Multiple Power-Saving Sleep Modes
- Lighting and motor control (PWM specific) controller models
- CAN controller support
- USB controller support
- Ethernet controller support
- LCD controller support
- Low-voltage devices operating down to 1.8 V (to 0.7 V for parts with built-in DC-DC upconverter)
- picoPower devices
- DMA controllers and “event system” peripheral communication.
- Fast cryptography support for AES and DES